This application claims the priority benefit of Taiwan application serial no. 90109255, filed on Apr. 18, 2001.
1. Field of the Invention
The invention relates in general to a method and a chipset for system management mode interrupt, and more particularly, to a method and a chipset for system management mode interrupt of a multi-processor supporting system.
2. Description of the Related Art
System management mode (SMM) is a special function of the central processing unit (CPU), such as a Pentium processor, used in a modern computer system. SMM provides the system designer with a method to control the computer via a firmware, such as a basic input output system (BIOS). SMM is also transparent to the operation system (OS). SMM has the following properties.
1. SMM has the system management interrupt (SMI) hardware interface. The chipset comprises a SMIOUT# pin. When the chipset enables the SMIOUT#, the central processing unit enters the system management mode to execute the system management interrupt handler routine prepared by the BIOS.
2. SMM has a private and safe memory space called system management random access memory (SMRAM) in which the SMI handler routine codes and the state dump area of the central processing unit are located. After entering the SMM mode, the firmware routine or the BIOS handler routine obtains parameter contents such as EAX and EBX of the CPU register from this state dump area while SMI occurs.
3. The system management mode base (SMBase) has a default address and can be reconfigured. In the multi-processor system, different CPUs can possess theirs specific SMBases.
4. The resume (RSM) command is used to leave SMM, and then CPU executes the next routine code when the SMI occurs.
BIOS can execute many system management interrupt handler routines under SMM to support functions that OS does not or does not fully supports. For example:
1. Support for a USB apparatus such as a keyboard or a mouse in OS DOS, or NT4.0. Neither OS DOS nor NT 4.0 has a USB driver to handle the USB apparatus and controller. Therefore, the chipset has to compromise with the BIOS to provide the SMI hardware interrupt interface and the handler routine to trap IO port (60h or 64h) of the conventional keyboard controller (such as 8042). Then BIOS can emulate the functions of the USB apparatus and the controller. Thus, under OS DOS and NT 4.0, the USB apparatus can be used without the USB driver.
2. Support for the advanced power management (APM) apparatus. BIOS provides OS with INT15 and software SMI to manage the power source to save power and implement a power saving mode operation.
3. Support for the special function of motherboard. Many motherboard designers design special functions and use SMI handler routine to implement special hardware operation.
The interrupt trap of the I/O port (IO trap) is the key source of SMI and can be used to support early AP or game (under DOS or NT 4.0) to use newer apparatus such as an USB keyboard or mouse. Conventional keyboard controller (8042) has two IO ports, a command port 64h and a data port 60h. Some early application programs (AP) or games (under DOS or NT 4.0) intended to control the early 8042 keyboard and mouse directly. However, the early AP and games were unable to use any USB apparatus because the USB controller is different from the early keyboard controller (8042). However, it is proven that the USB apparatus is more and more popular and widely applied. Fortunately, via SMI handler, the chipset can trap the command port 64h or the data port 60h to generate SMIOUT# to the CPU. Thus, the SMI handler of the BIOS can use program to control the USB keyboard. Via the IO trap mechanism, the USB apparatus can be used normally in an AP or game developed under early OS DOS and NT 4.0 Windows operation system without USB driver.
Such SMI apparatus can operate normally in a single CPU system. However, when applied in a multi-processor system under an operation system such as NT 4.0 Windows operation system, remediless errors may occur.
For example, in a two-CPU system and under the NT 4.0 Windows operation system that uses USB keyboard, when SMI occurs, these two CPUs store all the register data into the individual state dump area in SMRAM and enter the system management mode. In the system management mode, only one CPU (the first CPU hereinafter) executes SMI handler routine. The other CPU (the second CPU hereinafter) is in a loop and stands by for the first CPU to complete SMI handler routine and to inform the other CPU to execute RSM command, so that these CPUs are retrieved to the states before SMI, and then these CPUs can execute their individual previous next commands.
If, before entering the SMI mode, the second CPU is executing an NT 4.0 Windows operation system program to access the IO port of the conventional keyboard controller (for example, Assembly codes of OUT 60h, AL or OUT 64h, AL command), the south bridge chip detects the IO port of the conventional keyboard controller at the peripheral component interface (PCI) bus to extract the command data, address data and the byte enable data, and stores these data in the register thereof. When the system is not actually connected to the conventional keyboard, the south bridge chip enables a system management interrupt signal (SMIOUT#), so that the first and second CPUs enter the system management mode simultaneously. Meanwhile, if the SMI handler routine is executed by the second CPU, the second CPU can then execute according to the command, address, the extracted byte enable data, and the IO data in the state dump area of the second CPU (the parameters of AL, AX, or EAX register). However, the SMI handler routine is in fact executed by the first CPU. The first CPU cannot recognize whether the IO data (parameters) are stored in the state dump area of the first or the second CPU. When the SMI handler routine is executed under these circumstances, the first CPU may operate un-correctly to cause unexpected results.
Therefore, without knowing which CPU is executing access of the command port 64h or the data port 60h, the SMIOUT# generated by the chipset is given to all the CPUs. As a result, all the CPUs enter the SMM. As the first CPU executes the SMI handler routine, other CPUs stand by. However, as the first CPU does not know whether the IO data (parameters) is stored in its state dump area or in the second CPU""s state dump area, then errors may occur.
The invention provides a method and a chipset for system management mode interrupt of a multi-processor supporting system, to resolve the parameter access problem occurring in the system management mode operation of a multi-processor system, and to avoid system errors.
In the method for system management mode interrupt of a multi-processor supporting system, the multi-processor supporting system comprises a plurality of CPUs, a PCI bus and a chipset. The CPUs comprises a first CPU and a second CPU. When any of the CPUs is executing a software program to access a specified IO port defined by the chipset, the chipset detects the specified IO port at the PCI bus and extracts the trap data to store in the chipset. The chipset enables the system management interrupt signal. The first and the second CPUs enter the system management mode according to the system management interrupt signal. The first CPU executes a proper operation according to the trap data stored in the chipset, while the second CPU waits until the proper operation is complete. After the proper operation is complete, the second CPU is informed by the first CPU. The first and second CPUs then return to their original state, the state before entering the system management mode, to execute a previous next command individually. In one embodiment of the invention, the software program is a program executed under NT 4.0 Windows operation system.
The invention further provides a chipset of multi-processor supporting system. The multi-processor supporting system comprises a plurality of CPUs and a PCI bus. The CPUs comprises a first CPU and a second CPU. The chipset comprises a first register set, used to store the command data, the address data and the byte enable data, and a second register used to store the IO data (parameters). When any of the CPUs is executing a software program to access a specified IO port defined by the chipset, the chip detects the specified IO port at the PCI bus and extracts the command, address and byte enable data to store in the first register set. Meanwhile, the chipset further extracts the IO data (parameters) to store in the second register. The chipset then enables the system management interrupt signal, so that the first and the second CPUs enter the system management mode. The first CPU executes a proper operation according to the command data, the address data, the byte enable data and the IO data stored in the first and the second registers. After the first CPU executes the proper operation, the second CPU is informed. The first and the second CPUs return to their original state, the state before entering the system management mode, and execute a previous next command respectively.
In the invention, when the specified IO port defined by the chipset is accessed by the system, it is detected by the chipset at the PCI bus. Meanwhile, a trap data is extracted by and stored in the chipset. Therefore, when the multi-processor system is in the system management mode, the CPUs can access the correct data (parameters) from the chipset to execute a proper operation. The system can thus operate normally.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.